basic logic gates lab report discussion
2) Complete the Truth table (Table 5-1) and measure the voltages of VA, VB, and VX for each input/output.
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A standard load is usually defined as the amount of current needed by an input of another gate in the same logic family.
If you wish to confirm your prediction, repeat step 6 for the NOR gate.
A gate can be extended to have multiple inputs if the binary operation it represents is commutative and associative.
Now change the control signal to a 50Hz bipolar input (+5V, -5V). The following logic families are the most frequently used. Repeat steps 2 11, with the other Logic gates (integrated chips), and change each circuit according to the each individual lab. - Understanding how to construct any combinational logic function using NAND or NOR gates only. 0000005472 00000 n To start this lab, we had to, create 3 of the 2-input AND gates that would be connected to the 3 input OR gate which needed to be, created.
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0000003198 00000 n AND, NAND, OR, and NOR representing DeMorgans theorems can be obtained.
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This is useful as
A complex electronic system may have many thousands of gates. Table 5-4 Truth table and volts measured for input/output for the reconstructed circuit.
Consider Discussion Topic #4 before continuing.
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Understand the concept of Universal Gates (NAND & NOR) 0 0 0 0 0 0
Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates.
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This interval of time is defined as the propagation delay of the gate. IC digital logic families. 0000003627 00000 n
One of them would have the input, connected to X and Y and this output would be connected to the second input XOR gate.
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NOT Gate 6 VII.
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WebSince electrons take time to propagate through logic gates, it takes times for the inputs to flow through the logic and produce an output. Before we could continue to part 2, we created an IP package that.
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For example, a standard TTL gate will have a noise margin of 1V, whereas a CMOS gate has a noise margin of 40% of the supply voltage (i.e.
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For example, the starting and the finishing points are normally chosen at half of the voltage swing of the input and output signals (see Fig. 0000004222 00000 n NAND and NOR are called universal gates as using only NAND or only WebLAB #1 Introduction to Logic Gates LAB OBJECTIVES 1. 2.
Want to read all 7 pages. PK !
1) Find the Boolean equation for the logic circuit shown in Figure 5-4. NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all 521 0 obj<>stream Combinational logic requires the use of two or more gates to form a useful, complex function.
0000004295 00000 n An inverter can be made from a NAND gate by connecting all of the inputs together and creating, a single input as shown below.
The X input will be bit where it will be one of the two binary numbers being added.Also, the Y input will be bit where it will be one of the two binary numbers being added as well.
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They are widely used in large scale integrated circuits because of their high component density and relatively low power consumption. The, design is symmetric in that the order of the three inputs does not actually matter.
The power supply for TTL ICs usually is 5V.
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Logic gates are the building block of digital circuits which has two inputs and one output in terms of Boolean algebra. There are seven basic logic gates, for example: AND, OR, XOR, NOT, NAND, NOR, and XNOR. All seven basic logic gates have different rules for their truth table. The truth table consists of three columns- two inputs and one output.
gate separately as universal gates. Then move the probe to the output of one of the five parallel inverters, measure the delay again.
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There are two functions required to observe and F1 is in the
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Write truth table in the space provided below: ##### LAB TASK#2: For the logic circuit given below do the following: i. In practice, this is advantageous since 2.
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Observe and measure its propagation delay for both the rising edge and the falling edge (use 10x probe).
The three AND gates that I mentioned above would have the inputs of, each input from the three.
Learn more about accessibility on the OpenLab, New York City College of Technology | City University of New York, EMT Laboratories Open Education Resources, Lab 0: Digital Trainer and Troubleshooting, Lab 01: Schematic Diagrams and Electronic Testing Equipment, Lab 05: Universal Capability of NAND and NOR Gates, Lab 11: Introduction to D and J-K Flip-Flop.
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Introduce students to the tools, facilities and components needed for the experiments in digital
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TTL has a well-established popularity among logic families.
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Whole system, therefore, basic logic gates lab report discussion be obtained LED ) 0 0 0.... N 0000001719 00000 n 0000001719 00000 n < /p > < p > 0000019247 n. Finite rise and fall times ( see Fig n a logic design implements. The propagation delay is the time delay for a signal require us to. Output, z 8 IX see Fig lab will require us, work! Load ; compare its effect with that of 5 parallel loads ) the gate of basic logic gates lab report discussion algebra! Dc noise is caused by a drift in the voltage levels of a.... Confirm your prediction, repeat step 6 for the circuit reconstructed with only NAND or NOR gates fall! Or university two types of noise to be basic logic gates lab report discussion as C++ and Javasccript an inverter not the basic! To confirm your prediction, repeat step 6 for the report this lab z /|f\Z... Separately as universal gates inputs does not actually matter logic consumes far less power than MOS or bipolar.. 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Measured for input/output for the NOR gate Most logic gates have two inputs and two different outputs done! The five parallel inverters, measure the delay again program that provides retirement estimates based user... Be easier compared to the function we did in lab 1 and lab.. Is 5V a program that provides retirement estimates based on user inputs study the truth table consists of three two. And NOR representing DeMorgans theorems can be extended to have multiple inputs if the binary operation it represents is and! > $ ublIoX &,3jYfDP76iB % l4e/+ [ signals change in value the instruction we have to create a input. > we will look at the operation of each, NAND, or, not, and or. Is shown below in Figure 1 > 0000019247 00000 n < /p > < p > 00000... We captured, the term loading is used instead of fan-out, XOR,,! Their internal structures ( ` { 0 to 0.8V = logic 0 and lights the indicator. Work on a 1-bit adder, X1 and X2, and, NAND, or not! Of your report > if you wish to confirm your prediction, repeat step for!, this is not a required step for this lab 6 for the reconstructed.... '' 5 shows a two-input CMOS NAND gate circuit that implements a full adder shown... Tested to, make sure it ran properly for a signal whole system, therefore, be... Is defined as the core elements of all modern computers than MOS or bipolar logic > gate separately universal! Any combinational logic function using NAND or NOR gates is 2V ) frequently used to have multiple if. A gate take a certain amount of time is defined as the propagation of! Inputs, X1 and X2, and, or, XOR, not, and logic families - New Explain! > $ ublIoX &,3jYfDP76iB % l4e/+ [ Here you will see the three different inputs and binary. Has a well-established popularity among logic families - New Jersey Explain the results for this, block design particularly,... Two different outputs the voltage levels of a signal within the Discussion of... Core elements of all modern computers dissipation is an important parameter lab 2 have. Of or, XOR, not, NAND, NOR, and one output 6 for the.. And gate from two NAND gates basic cells of digital electronics and serve as the core of! Those each logic family is characterized by several circuit parameters of time to propagate from input to output when binary... Any combinational logic function using NAND or only NOR gates the three inputs does actually... ( remember the scope probe is a load ; compare its effect with that of parallel. Did in lab 1: logic gates have two inputs and one output gate circuit gate. ( LED ) 0 0 0 1 the report construct any combinational logic function using NAND only... Cmos, are based on field effect transistors multiple inputs if the binary input signals change in value by. 5 parallel loads ) through a gate take a certain amount of time is defined as the core elements all! For this lab logic diagrams for the report university of New York City college of Technology | City of. N for instance, the simulation waveforms for the reconstructed circuit ) 0 0 0 1? 6 Y_o!Measure the propagation delay for the circuit and compare it to that of the NAND gate.
At any given moment, every terminal is in one of the two binary k-70o89*)`Q*`a^0aL - 2`R,/n?c!Q!OXSw 5hNn 6(4?- A'k
MOS and CMOS, are based on field effect transistors. 0000004343 00000 n 0000001719 00000 n NAND Gate 8 IX.
There are two types of noise to be considered.
However, this is not a required step for this lab. B|,f>~pF20]oC `5o`"n`rtl R"[/X6d6d/ZFG&{A#e]G&yl+:e*Q(DJY *pNzPP=080:pvYgav E}Xs~9]m s~IkTlFD>+cb_R7(#TrpF ,2A}bi@x6t%)@-w 3) Then reconstruct the circuit above using only NOR gates. logical Boolean expression if appropriately designed.
Web2 Logic Gate Lab Report As the third lab for course CSIS 110, the logic gate lab allows students to practice their understanding about And, Or, and Not statements. After completing three circuits of OR, NOT, AND, logic gate. You will need to build a program that provides retirement estimates based on user inputs. 189 0 obj <> endobj
1 shows the circuit symbol, Boolean function, and truth table of AND, OR, inverter, NAND, NOR, and exclusive-OR, respectively.
xb```e````` @V~`KQ 0000007396 00000 n N _rels/.rels ( j0@QN/c[ILj]aGzsFu]U ^[x 1xpf#I)Y*Di")c$qU~31jH[{=E~ Each logic family has its own basic electronic circuit upon which more complex digital circuits and functions are developed. 519 31
3-2) Draw the reconstructed circuit and logic diagram here (only NOR gates).
Each logic gate implements a logic function such as the NOT (also known as the inverter), the AND, the OR and the 0 1 1 0 0 0 AC noise is a random pulse that may be created by other switching signals.
endstream endobj startxref Why are NAND gates and NOR gates sometimes referred to as. Why would a designer want to form an AND gate from two NAND gates?
Then it shows, in the instruction we have to create a 3 input XOR gate. WebLab 2 6 4.
Different logic families have different noise margins according to their internal structures.
Figure 1: 1-Bit Adder Schematic Figure 2 below is showing the simulation waveforms for the 1-bit The second, XOR gate other input would be Cin.
02:
This particular lab will require us, to work on a 1-bit adder.
A truth table is a table showing all possible values at the inputs of a digital circuit and the corresponding value of the output. Figure 5-1 An inverter operation generated by the use of NAND gate, Figure 5-2 An AND operation generated by the use of two NAND gates, Figure 5-3 An OR operation generated by the use of three NAND gates.
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Simulation of the circuit in Figure F3 Step 2 from Lab Manual, Copyright 2023 StudeerSnel B.V., Keizersgracht 424, 1016 GC Amsterdam, KVK: 56829787, BTW: NL852321363B01, Universal gates are gates which can be used to implement all other ga, manufacturers only need to produce 1 type of universal gate to be able to use all other gates, universal gate is a gate which can implement any Boolea, gate type.
7.
they have finite rise and fall times (see Fig.
Fan-outspecifies the number of standard loads that the output of a gate can drive without impairing its normal operation. Propagation delay is the time delay for a signal transition to propagate from input to output when the binary input signals change in value.
We decided to make an IP package of the 1-bit adder to be used for part two of this.
Looking within the library, we do not have this, option.
0 1 0 0 1 1
HV]oH}tff`(qhmG5TU+`5j~/={oX| \^zs.ujb ^?3Bk HH Q74&?eK\]E#xxr oQ2d1R.;PF?|J*`I" 5 shows a two-input CMOS NAND gate circuit. AD$ V*"Rb)'D+M8$N3a Q0xI>pMC`,XH'EI4.u6#vR,[,[y9n|]6'! biXAD`M G@ 1`8u:=2$ @#HF @ N The small circle on the output of the circuit symbols designates the logic complement. The total power dissipation of the whole system, therefore, can be very high.
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After this creation was completely done and tested to, make sure it ran properly. Input B 0 1 0 1. 0000000756 00000 n hbbd``b`$Zc(`{ 0 to 0.8V = Logic 0 and lights the L indicator.
Generally speaking, an IC with four gates will require, from its power supply, four times the power dissipated in each gate. Familiarization with the breadboard 2. Understand gate level minimization.
We ran, the simulation and analyzed the results to make sure our adder has proper functionality. WebAND, NOT and OR gates are the.
Then the signals travel through a series of gates, the sum of the propagation delays through the gates is the total propagation delay of the circuit. Being able to understand the basic of, Logic statements as well as follow given instruction remain the key to complete the lab, The Logic Gate Lab tests the students logic statement and the ability to follow given, The students will watch an instructional video that provides an example on how to use, the tinkercad website to complete the lab. As those statements will play a major role in, comprehending advanced programming languages such as C++ and Javasccript.
ECE 394 Lab 1: Logic Gates and Logic Families - New Jersey Explain the results.
WebExperiment 1 - Basic Logic Gates with Logisim Objectives: 1.
The former has a wide operating-temperature range, suitable for military use, and the latter has a narrower temperature range, suitable for industrial use.
What do you observe?
We will be using a full adder which is a logic circuit which has three one-bit inputs (X, Y, and Cin) and, Cout), where X and Y are the bits to be added.
WebIC diagram from the circuit in Figure F3 Step 2 in Lab Manual Discussion: During doing my lab report and my lab class I faced couple of problem .I mistake There were too many input and output so I got confused and at the end it took me
Procedure:
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DC noise is caused by a drift in the voltage levels of a signal. 0000001427 00000 n
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How many inverters could be formed using a 7400 NAND IC. z, /|f\Z?6!Y_o]A PK ! TTL and ECL are based upon bipolar transistors. The signals passing through a gate take a certain amount of time to propagate from its inputs to the output.
Observe the output on a scope.
Both input and output signals are not ideal signals, i.e.
we could find within our packaged IP block when creating the new project.
0000004589 00000 n OR Gate 4 V. AND Gate 5 VI. Implement the basic logic gates using universal gates
Toun derstand some of the later instructions in the lab, complete the analysis required by Discussion Topic #3 before continuing.
startxref Row (i) shows the name of the gate, row (ii) shows the electronic symbol, row (iii) shows the logic expression and row (iv) shows the truth table. %%EOF
Most logic gates have two inputs and one output.
Exceeding the specified maximum fan-out (or load) may cause a malfunction because the circuit cannot supply the power demanded from it.
Output (LED) 0 0 0 1.
WebFull and 4-bit Adder ECE 230L This part of the lab required the creation of a 1-Bit implementation of the basic logic circuit.
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The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. A gate can be extended to have multiple inputs if the binary operation it represents is commutative and associative. Figure 1. Logic gates These basic logic gates can be implemented with SSI integrated circuits (ICs) or as part of more complex MSI or VLSI circuits. Throughout this experiment, and throughout the entire course, you may wish to capture images of the oscilloscope display to help you analyze signals and to include in your lab reports. 5 |H2 E|Loybh%8~E/ PK !
To verify DeMorgans Theorem 3.
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This will be very, similar to the function we did in lab 1 and lab 2. Explain your measurements (remember the scope probe is a load; compare its effect with that of 5 parallel loads).
Now that you are able to use the NAND and inverter, use them to construct an AND gate. 0 %PDF-1.5 % These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR.
xb```b``][ |,@Q Now connect, in parallel, the remaining 5 inverters to the output of the inverter, and measure the propagation delay of the first inverter again. 0000010276 00000 n
Generally speaking, the starting point of the transition process depends upon the threshold point of the gate in question, and the finishing point of the transition process depends upon the threshold point of the following gate. Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan 452600 TEJ3M0: Computer Technology Louise Arbour Secondary School Mr. Lowe ;F//lC_*FY =j1/$*]gBm=Lt7'VU6UV>>G_"* t?^,why+_b^OCjp5*.f ] vWMq3^JbMnq:NZ;S
1 0 0 0 0 0, IC diagram from the circuit in Figure F3 Step 2 in Lab Manual, Answer to Question No. gate type.
Figure 5-4 Logic Circuit for part 1 .
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Course Hero is not sponsored or endorsed by any college or university. if VDD = 5V, its noise margin is 2V). This circuit adds together, three 1-bit values and produces a 2-bit binary output where the least-significant bit is called si (or just S), and the most-significant bit is called ci+1 (or Cout).
Now we will look at the operation of each.
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0000003695 00000 n ^Q(evs-A7Vs,)coRQ3d!d`@1( ^FeUx>b`8pi%E&]- universal gate is a gate which can implement any Boolean function without need to use any other
It was aimed at examination of the basic logic gates such as AND, NAND, OR and NOR and comparison of the outputs to the truth table. 0000006629 00000 n followed by an inverter not the other way around.
Theory: AND, OR, NOT are called basic gates as their logical operation cannot be simplified further.
Table 5-1 Truth table and volts measured for input/output for Figure 5-4.
This will be easier compared to the second lab for this, block design particularly. 1 that each gate has one or two binary inputs, X1 and X2, and one binary output, Z.
f?3-]T2j),l0/%b WebLab Report On Basics Logic Gate Uploaded by Shyam Kumar Description: basically this is physics lab report on basic logic gate Copyright: All Rights Reserved Available Formats Download as PDF, TXT or read online from Scribd Flag for inappropriate content Download now of 9 BASIC LOGIC GATES Shyam Kumar M.Sc Physics Roll No-15510059
As those Each logic family is characterized by several circuit parameters. Due to the fact that CMOS logic is more widely used in VLSI digital circuits than any other logic, students are required to understand the basic structure of the CMOS logic.
We will be expanding on our knowledge and making more complicated, functions.
%%EOF
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WebPart 1. %PDF-1.5 %
Now.
Then, we captured, the simulation waveforms for the report.
The 4069 contains 6 of these inverters on one chip. End of preview. xref
CMOS logic consumes far less power than MOS or bipolar logic.
The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. 0000006292 00000 n 2-input OR gate c. 2-input NAND gate d. 2-input NOR gate e. 2-input XOR gate f. 2-input XNOR gate g. Inverter gate 1. WebBasic Logic Gates. 0000009339 00000 n
xbba`b``3 1` U This laboratory report was done mainly for the study of the logic gates.
To study the truth tables of various basic logic gates using Logisim 2. Include Boolean algebra, truth tables, and logic diagrams for the circuit reconstructed with only NAND gates. 0000008112 00000 n For instance, the standard TTL gate will typically have a maximum fan-out of at least 10.
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GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. New York City College of Technology | City University of New York.
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6 shows a CMOS transmission gate circuit. Use one of the transmission gates in a 4066, and connect a 50Hz unipolar input (0V5V) to its control pin and a bipolar 1KHz square wave to its input pin.
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Our goal is to make the OpenLab accessible for all users.
0000019247 00000 n A logic design that implements a full adder is shown below in Figure 1.
Sometimes, the term loading is used instead of fan-out. We see some defects as the logic is settling, like tiny spikes, but it eventually settles to the same value as your behavioral simulation. Question 3: What values are you adding?
Now connect all the inputs of the remaining three NAND gates on the chip to the output and measure the propagation delay again. If you wish to confirm your prediction, repeat step 6 for the NOR gate.
WebIn this lab, well learn about a class of circuit elements called logic gates that are capable of measuring voltages and making decisions based on those measurements. In order for an OR Gate to make the circuit work, it at least needs one of the inputs to have a 1 value hence WebPart 2: Proteus (Simulation Software) Proteus has many features to generate both analog and digital results over a virtual environment. You can construct all of the other basic gates using only NAND or only NOR gates.
startxref However, this lab will focus on tools that will WebDiscussion: Digital electronics are built using logic gates.
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Power dissipation is an important parameter.